1. Field of the Invention
The present invention is directed in general to receivers for processing multiple input signals. In one aspect, the present invention relates to a method and system for servicing two satellite signals by multiplexing two fully independent IDE channels over common pin input/outputs. In a further aspect, the present invention provides an integrated circuit system for multiplexing the data, address, and chip select lines of the IDE interface so that twice as many hard drives may be interfaced using the common pins of the integrated circuit.
2. Related Art
In the context of providing for data storage and retrieval, bus interface standards have been developed, such as the Advanced Technology Attachment (ATA) standard interface for hard disk drives that controls the flow of data between the processor and the hard disk. The standard has also been referred to as Integrated Drive Electronics (IDE), and the one following it is called Enhanced Integrated Data Electronics (EIDE). The ATA standard defines a command and register set for the interface, creating a universal standard for communication between the drive unit and the PC. The standard was extended to working with CD-ROMs and tape drives, the extension being known as Advanced Technology Attachment Packet Interface (ATAPI), the full standard now being known as ATA/ATAPI. This standard has evolved through different versions, including AT Attachment with Packet Interface-5. This standard includes new ultra DMA modes to define transfer rates of 44.4 and 66.7 MB/s, and also made mandatory use of an 80-conductor IDE cable for UDMA modes 3 and 4. In addition, proposals have been made for ATA Host Adapter Standards to specify an open host controller interface for ATA host adapters, wherein different types of host adapters, methods for their identification, and the programming interfaces used are defined.
A significant contribution to the overall cost of manufacturing integrated circuits is the pin count. The standard ATA requires at least 27 pins per channel. Under conventional approaches, extra pins are required for each channel, or alternatively, pins are shared during channel storage, such that one channel has exclusive access to the ATA bus until a DMA data transfer is finished, after which time the second channel obtains exclusive access. As a result, the throughput over such a bus will be approximately half of that of the independent 2-channel ATA bus system which provides separate pins for each channel. It is therefore desirable to find a way to regain some of this loss in maximum throughput. It is also desirable to keep pin count to a minimum.
In addition to meeting reduced chip space and pin count requirements, the ever-increasing need for higher speed communications systems imposes additional performance requirements and resulting costs. In order to reduce costs, communications systems are increasingly implemented using Very Large Scale Integration (VLSI) techniques. The level of integration of communications systems is constantly increasing to take advantage of advances in integrated circuit manufacturing technology and the resulting cost reductions. This means that communications systems of higher and higher complexity are being implemented in a smaller and smaller number of integrated circuits. For reasons of cost and density of integration, the preferred technology is CMOS.
Further limitations and disadvantages of conventional systems will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.